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Chapter 3: Functional Description
Device-Level Description
Figure 3–6. Cyclone II DQS Group Block Diagram
(Note 1) (2)
3–11
doing_ w r
D
Q
d q _oe
DQ_A OE
D Q
8
w data
D
16
E N
Q
D
Q
Ao
0
d q
w data_ v alid
D
Q
D
Q
1
Bo
E N
w rite_clk
8
Q
D
Q
D
A I
resynch_clk
resynched_data
Optional Inverters (Note 4)
E N
rdata
8
Q
D
Q
D
Q
D
16
Preset (asynchronous)
C I
E N
B I
D
Q
d q _ena b le_reset
postam b le_clk
D
Q
d q _ena b le
Optional Inverter (Note 4)
(Note 3)
d q _capt u re_clk
Clock Control Block
Clock Delay
Control Circ u it
Delay
doing_ w r
d q s_oe
DQS_A OE
D Q
D
Q
d q s_ bu rst
B OE
D
Q
D
Q
0
d q s
2
D
Q
1
b e
D
Q
doing_ w r
E N
D
Ao Q
0
dm
D
Q
D
Q
1 1
Bo
E N
IOEs
FPGA LEs
w rite_clk
altddio Megafunctions
Notes to Figure 3–6 :
(1) This figure shows the logic for one dq output only. A complete byte group consists of eight times the DQ logic with the DQS and DM logic.
(2) All clocks are clk , unless marked otherwise.
(3) Each DQS requires a global clock resource. Invert combout of the ALTDDIO_BIDIR megafunction for the DQS pin before feeding in to inclock
of the ALTDDIO_BIDIR megafunction for the DQ pin.
(4) The optional inverters are controlled by the resynchronization edge and postamble edge settings on the Manual Timing tab, refer to “Manual
Timing Settings” on page A–1 .
? March 2009
Altera Corporation
DDR and DDR2 SDRAM Controller Compiler User Guide
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